This invention relates to data sampling and analysis. More particularly, this invention relates to implementing data sampling and analysis within a programmable logic resource.
Programmable logic resource technology is well known for its ability to allow a common hardware design (embodied in an integrated circuit) to be programmed to meet the needs of many different applications. Known examples of programmable logic resource technology include programmable logic devices (PLDs), complex programmable logic devices (CPLDs), erasable programmable logic devices (EPLDs), electrically erasable programmable logic devices (EEPLDs), field programmable gate arrays (FPGAs), application-specific standard products (ASSPs), and application-specific integrated circuits (ASICs).
To facilitate the use of programmable logic resources in certain applications, intellectual property (IP) blocks are coupled to programmable logic resource core circuitry. In one application, an IP block is a block of logic or data that supports a multi-channel communications protocol such as high speed serial interface (HSSI) communications. HSSI communications include (1) industry-standard forms such as XAUI, PCI Express, InfiniBand (IB), Fibre Channel (FC), Gigabit Ethernet, Packet Over SONET or POS-5, Serial Rapid I/O, etc., and (2) any of a wide range of non-industry-standard or “custom” forms that particular users devise for their own uses. Such custom protocols often have at least some features similar to industry-standard protocols, but deviate from industry standards in other respects. In a multi-channel communications protocol, data transfers to and from the programmable logic resource core circuitry and the IP block over multiple channels.
An increasingly important type of signaling between devices is “clock data recovery” or “CDR” signaling. In CDR signaling, the clock signal information is embedded in a serial data stream so that no separate clock signal needs to be transmitted. For example, data may be transmitted serially in “packets” of several successive serial data words preceded by a serial “header” that includes several training bits having a predetermined pattern of binary ones and zeros. The clock signal information is embedded in the data signal by the high-to-low and/or low-to-high transitions in that signal, which must have at least one high-to-low or low-to-high transition within a certain number of clock signal cycles. At the receiver the clock signal is “recovered” from the data signal. The clock signal is then used to recover the data from the data signal.
Analysis is typically performed on the serial data stream by connecting external equipment to the input data pins on the programmable logic resource. The serial data stream is sent as input to equipment such as an oscilloscope, a logic analyzer, or a time interval analyzer (TIA). An oscilloscope is an instrument that displays and analyzes the waveform of analog signals such as voltage or current as a function of time. A logic analyzer is an instrument that displays and analyzes the waveform of digital signals such as voltage or current as a function of time. A TIA is an instrument that measures the time interval between signal pulses. The equipment samples and processes the serial data stream to generate an output signaling, for example, the time between input pulses and the widths of data high or data low pulses. The processed data is then typically sent as input to the programmable logic resource for further processing by the core circuitry.
Performing data stream analysis requires the use of bulky external equipment. Because the equipment is generally not provided with the programmable logic resource, the user of the programmable logic resource is required to have the equipment accessible. In addition, the user is required to manually locate the input data pin on the programmable logic resource, connect the pin to the input of the equipment, and connect the output of the equipment back to the correct pin on the programmable logic resource.
In view of the foregoing, it would be desirable to provide sampling and analysis of data streams within the programmable logic resource without the use of external equipment.